1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to an integrated circuit structure containing both an MOS device and a bipolar device and a method of constructing both devices on a substrate at the same time.
2. Description of the Prior Art
The use of MOS devices, in preference to bipolar devices, usually occurs when either the low power consumption or high density characteristics of MOS devices are needed or desired. However, an MOS device is usually constructed in a non planarized fashion with steps created when making contact with the source and drain regions which are lower than the gate region. Furthermore, despite the high density of the MOS devices, the gate contact usually occupies a large area due to the need to make the contact in a position offset to the gate region because of alignment problems.
In the construction of MOS devices, the source and drain junctions may be formed too deep causing the junctions to sometimes extend under the gate region causing overlap capacitance which degrades the performance of the device. The extension of the junction under the gate may be caused by forming the junction too deeply in the substrate. This can also cause the depletion region to extend sideways into the channel causing a short channel effect which further degrades the performance and functionality as well as long term reliability. If the source and drain regions can be formed as shallow junctions, which do not extend laterally, e.g., beneath the gate, the junction capacitance may also be lowered because of the reduction in the junction area.
On the other hand, bipolar devices may be chosen instead of MOS due to their high current carrying characteristics and superior transconductance. However, the use of an extrinsic base to provide interconnection between the intrinsic base and the base contact adds undesirable resistance as well as additional capacitance to the device which degrades performance. Furthermore, the construction of bipolar devices on a substrate can also result in the creation of undesirable steps resulting in the need for further planarization steps.
In many instances, it would be most desirable to use both types of devices in an integrated circuit structure to achieve certain desired effects, e.g., fast logic and low power storage. However, this may be difficult due to the differences in the techniques which have evolved to construct bipolar and MOS devices; particularly when such techniques may be addressed toward remedying a problem which is peculiar to one particular device.
It would, therefore, be very desirable to be able to construct both bipolar and MOS devices on the same substrate and to be able to construct the devices in a manner which would address the problems of the particular devices discussed above including the construction of a planarized integrated circuit structure incorporating such devices therein.